A low power voltage level shifter (LS) design is presented in this paper. A regulated cross coupled (RCC) pull-up network is utilized in this design in order achieve high speed and low power ...

Figure 1. Implementation of a level shifter. Figure 2 shows a standard NTSC composite test-video signal (color-bar signal generated with a Tektronix 1910 digital generator), to which a DC offset is ...

I'm looking for a digital logic level translator and was wondering if you had any recommendations. Basically, we need to shift a 1.5V signal on a 100MHz clock up to a 3.3V signal. We would also like ...