GitHub2mon
This is a DDR3 SDRAM (MT41K128M16JT-125) sample project for Arty A7-35T FPGA board.
The recommented version is Vivado 2024.1. When creating a Vivado project, please select xc7a35ticsg324-1L as an FPGA. Please add main.v and main.xdc to your Vivado project. This code will explain what ...
Design-Reuse17y
Xilinx Virtex-5 Devices First FPGAs in Production to Demonstrate Interoperability with DDR3 SDRAM Technology
SAN JOSE, Calif., July 31, 2007 – Xilinx, Inc. (NASDAQ: XLNX), the world’s leading supplier of programmable solutions, today announced that its Virtex™-5 FPGA devices are interoperable with 800 Mbps ...
Design-Reuse1mon
DDR3 SDRAM Controller supporting Altmemphy
The Altera® DDR3 SDRAM High-Performance Controller MegaCore® functions provide simplified interfaces to industry-standard DDR3 SDRAM devices and modules. The MegaCore functions work in conjunction ...
GitHub1y
AXI DDR3 SDRAM Memory Controller for Xilinx GoWin Altera Intel Lattice FPGAs, written in Verilog.
The reason for operating in DLL=off mode is so that the DDR3 clock frequency can be chosen per-application ... indicating that the the burst-operation is part of a sequence of such, to the same SDRAM ...
Texas Instruments3y
AM335x with DDR3 - routing guidelines and device speed questions
Also, are there simulations that show serial termination will not work? I have a reference schematic from TI called Frost Byte which has DDR3 SDRAM with serial termination. Has that board been built?
Texas Instruments2y
DM8168 DDR3 init problem: jtag fails
Im trying to initialize a DDR interface on a custom board with DM8168 and DDR3 Micron MT41J128015E. I'm using Spectrum Digital XDS200 debugger and CCS 5.2.1 for debug. My board fails and DDR3 ...